Ariaboard Rockchip rk3308: Difference between revisions
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[[File:Smart4418-SDK-1606F1.jpg|thumb|500px|Front]] | [[File:Smart4418-SDK-1606F1.jpg|thumb|500px|Front]] | ||
==Dimension== | ==Dimension== | ||
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|Dimension || 50 x 50 x 4(mm) | |Dimension || 50 x 50 x 4(mm) | ||
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|Pitch || 1.27mm | |Pitch || 1.27mm | ||
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==Specifications== | ==Specifications== | ||
[[File:Smart4418-SDK-Features001.jpg|thumb|600px|Features]] | [[File:Smart4418-SDK-Features001.jpg|thumb|600px|Features]] | ||
Revision as of 04:57, 15 July 2021
Introduction
Dimension
Dimension 50 x 50 x 4(mm) Pitch 1.27mm
Specifications
System On Model Ariaboard Rockchip RK3308 CPU Rockchip RK3308 Quad Cortex®-A35 1.3GHz DDR 16bit DDR3L-1866 512MByte Flash eMMC-5.1 4GByte Audio Codec RK3308 build in codec Ethernet Realtek RTL8152B 10/100M PHY Display Interface RGB666 UART 5 CAN Bus 1 SPI 2 I2C 3 I2S 2 USB 2.0 2 SDIO 2 Power DC [email protected]
Diagram, Layout and Dimension
Pin Descriptions
- 26Pin UART/SPI/I2C/PWM Interface
Pin# Name Pin# Name 1 VDD_3.3V 2 VDD_5V 3 I2C0_SDA 4 VDD_5V 5 I2C0_SCL 6 DGND 7 NC 8 UART3_TX 9 DGND 10 UART3_RX 11 NC 12 GPIOD1/PWM0 13 NC 14 DGND 15 NC 16 GPIOC13/PWM1 17 VDD_3.3V 18 NC 19 SPI0_MOSI/GPIOC31 20 DGND 21 SPI0_MISO/GPIOD0 22 NC 23 SPI0_CLK/GPIOC29 24 SPI0_CS/GPIOC30 25 DGND 26 NC
- LVDS Interface
Pin# Name Pin# Name 1 SYS_3.3V 2 SYS_3.3V 3 GPIOC16 4 GPIOB18 5 DGND 6 DGND 7 LVDS_D0- 8 LVDS_D0+ 9 LVDS_D1- 10 LVDS_D1+ 11 LVDS_D2- 12 LVDS_D2+ 13 DGND 14 DGND 15 LVDS_CLK- 16 LVDS_CLK+ 17 LVDS_D3- 18 LVDS_D3+ 19 I2C2_SCL 20 I2C2_SDA
- DVP Camera Interface
Pin# Name 1, 2 SYS_3.3V 7,9,13,15,24 DGND 3 I2C0_SCL 4 I2C0_SDA 5 GPIOB14 6 GPIOB16 8,10 NC 11 VSYNC 12 HREF 14 PCLK 16-23 Data bit7-0
- LCD Interface
Pin# Name Description 1, 2 VDD_5V 5V Output, it can be used to power LCD modules 11，20，29, 37，38，39，40, 45 DGND Ground 3-10 Blue LSB to MSB RGB blue 12-19 Green LSB to MSB RGB green 21-28 Red LSB to MSB RGB red 30 GPIOB25 available for users 31 GPIOC15 occupied by FriendlyARM one wire technology to recognize LCD models
and control backlight and implement resistive touch, not applicable for users
32 XnRSTOUT Form CPU low when system is reset 33 VDEN signal the external LCD that data is valid on the data bus 34 VSYNC vertical synchronization 35 HSYNC horizontal synchronization 36 LCDCLK LCD clock, Pixel frequency 41 I2C2_SCL I2C2 clock signal, for capacitive touch data transmission 42 I2C2_SDA I2C2 data signal, for capacitive touch data transmission 43 GPIOC16 interrupt pin for capacitive touch, used with I2C2 44 NC Not connected
- SATA Interface
- Standard 7Pin Data Interface, 4Pin Power Interface
- File:SATA-01.png
- Power Interface
- DC power jack, applicable for DC 5.5 * 2.1mm power jack, DC 9V~24V/2A. When you connect a SATA hard disk or LVDS LCD to it a 12V/3A power adapter is required
- File:DC-005.png
- 2.54mm pitch, 2510-4P pin-header, Pin1~Pin4 description: VDD_12V, DGND, DGND, 12V_IN
Pin 12V_IN is connected to DC power jack, VDD_12V is connected to 12V_IN through the S1 switch
- 2.54mm pitch, 2510-4P pin-header, Pin1~Pin4 description: VDD_12V, DGND, DGND, 12V_IN
- File:CON5.png
Dimensional Diagram
- For more details refer to :dxf file
Resources
- SDK Carrier Board Hardware Technical Documents
- PCB source files, Allegro 16.5 or above
- PCB dxf file
- schematics, OrCAD 16.5 or above
- schematics in pdf
- PCB source files, Allegro 16.5 or above
- Smart4418 CPU board wiki
- Smart4418 CPU board schematics in pdf
Update Log
August-02-2016
- Released English version
Dec-08-2016
- Updated Section 2